TWO LEVEL STATE ESTIMATION BASED ON VERTICAL DIVISION STATE ESTIMATION TECHNIQUE FOR ELECTRIC POWER SYSTEM

UDUPA, H. NAGARAJA and KAMATH, H. RAVISHANKAR (2015) TWO LEVEL STATE ESTIMATION BASED ON VERTICAL DIVISION STATE ESTIMATION TECHNIQUE FOR ELECTRIC POWER SYSTEM. Journal of Basic and Applied Research International, 13 (1). pp. 8-32.

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Abstract

The State estimation computation is an integral part of power system Energy Management System (EMS). The state estimation for large-scale power system is highly complex and computationally slow. To enhance the computational efficiency, one of the methods suggested in the literature is “Two Level State Estimation (TLSE)”. Another recent publication [1] provides an unique solution called power system Vertical Division State Estimation technique (VDSE). In VDSE technique the measurements are grouped around the node clusters and processed independently, whereas in TLSE technique the power system network is sub-divided into smaller area such that each sub network can be processed independently. Interestingly, TLSE provides a network division technique while VDSE provides a computational task division technique around a node cluster. This paper presents a combination of TLSE and VDSE technique which has been called as Two Level state estimation based on Vertical Division State Estimation technique (TLVDSE). The major limitations of TLSE are i) the computational solution used in TLSE is ISE which is procedure oriented and hence, it is difficult to use multiprocessors in a given local area Ii) if the b-node injected power measurements are considered then for calculated injected power of a given local area the state variables of other connected local areas are needed. The TLVDSE addresses both the limitations of TLSE. The combination of TLSE and VDSE results in cancellation of second level (boundary node level) computations. The outcome of TLSE is analyzed by applying VDSE solution to each sub-network. The concept is tested on 30 bus IEEE system for TLVDE and compared with ISE and TLSE. The computational time comparison has also been carried out for 13, 14, 30 and 57 bus IEEE test systems and the results are tabulated.

Item Type: Article
Subjects: Eurolib Press > Multidisciplinary
Depositing User: Managing Editor
Date Deposited: 09 Jan 2024 06:58
Last Modified: 09 Jan 2024 06:58
URI: http://info.submit4journal.com/id/eprint/3255

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